Toshiba TLCS-90 Series Data Book page 13

TOSHIBA
TMP8048A/TMP8035A,TMP8049A/TMP8039A
PIN NAMES AND PIN DESCRIPTION
VSS (Power Supply)
Circuit GND potential
VDD (Power Supply)
+5V during operation Low power standby pin for TMP8048A RAM
VCC (Main Power Supply)
+5V during operation
PROG (Output)
Output strobe for the TXP8243P I/O exapnder
PlO-P17 (Input/Output) Port 1
8-bit quasi-bidirectional port (Internal Pullup
P20-P27 (Input/Output) Port 2
50 kohm).
8-bit
quasi~bidrectional
port (Internal Pullup
=
50 kohm).
P20-P23 Contain the four high order program counter bits during an
external program memory fetch and serve as a 4-bit I/O expander bus for
the TMP 8243P •
DBO-DB7 (Input/Output, 3 State)
True~idirectional
port which can be written or read synchronously using
the
RD,
WR strobes. The port can also be statically latched. Contains
the 8 low order program counter bits during an external program
mem~
fetch, and receives the addressed instruction under the control of PSEN.
Also contains the address and data during an external
RAM
data store
instruction, under control of ALE,
RD
and WR.
TO (Input/Output)
Input pin testable using the conditional transfer instructions JTO and
JNTO. TO can be designated as a clock output using ENTO CLK instruction.
Tl (Input)
Input pin testable using the JTl and JNTI instruction. Can be designated
the event counter input using the timer/STRT CNT instruction.
INT (Input)
External interrupt input. Initiates an interrupt if interrupt is
enabled. Interrupt is disabled after a reset. Also testable with
conditional jump instruction. (Active Low)
RD
(Output)
Output strobe activated during a Bus read. Can be used to enable data
onto the Bus from an external device. Used as a Read Strobe to External
Data Memory (Active Low).
WR (Output)
Output strobe during a Bus write (Active Low). Used as a Write Strobe to
External Data Memory.
MCU48-3