Toshiba TLCS-90 Series Data Book page 229

TOSHIBA
TMP90C840
Table 3.2 is a list of the bus operations for each instruction. Their
cycles (read, write or dummy) are indicated by symbols in the table.
Each bus cycle is represented by a single symbol (a character string
with one to three characters length) and delimited by a colon ":".
The bus operations should be read from the left to right.
A capital letter denotes an effective bus cycle, and a small letter (n
or d) denotes an invalid bus cycle. For example, data read out in the
read cycle of the "n" bus operation have no effect on the CPU
operation, and are ignored. The symbol "d" represents an internal
operation cycle that involves no read or write of memory.
Table 3.2 Bus Operations for Executing Instructions
Meaning of symbols
Symbol Data Bus Address Bus
N
Next Code Read Next Op Code Address
n Next Code Read (dummy)
Next Op Code Address
1
1 st Code Read Jump/Call/Return Address
2 2nd Code Read Op Code Address+1
3
3rd Code Read Op Code Address+2
4 4th Code Read Op Code Address+3
5 5th Code Read
Op Code Address+4
6 6th Code Read Op Code Address+5
d Dummy (No Read/Wri te) Undefined
R 1st Data Read 1 st Data Address
R+l 2nd Data Read 2nd Data Address
W 1 st
Data Write 1 st Data Address
W+l
2nd
Data Write 2nd Data Address
MPU90-31