System Flowchart - Toshiba TLCS-90 Series Data Book

TOSHIBA TMP90C840
3.2.5 System flowchart
Fig. 3.2 (6) is a system flowchart of the TMP90C840. A normal
operation repeats a loop between "Fetch instruction" and "Execute
instruction".
When an interrupt is acknowledged) the CPU proceeds to "Interrupt
processing". Executing the return instruction RETI makes the CPU
return to the address that follows the address of the SWI instruction
in the same way as the SWI instruction is executed under software
control.
When a HALT instruction is executed, the CPU suspends the operation
until an interrupt is requested. When the interrupt is acknowledged,
the CPU starts the interrupt processing. However, when a maskab Ie
interrupt is requested with the interrupt enable flag at "0"
(interrupts are disabled), the CPU only releases the HALT state and
starts executing an instruction that follows the HALT instruction.
For det ails of the interrupt proces sing, refer to "3.3 Int errupt
Function". The timing of releasing the HALT state is described in
"3.4 Standby Function".
By setting the RESET input level to "0", the CPU always returns to
"RESET" start position without regard to its current position in the
flowchart.
MPU90-28