Toshiba TC9349AFG Manual page 64

Cmos digital integrated circuit silicon monolithic
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I/O port input/output settings are determined at the I/O control data ports. Set the I/O control data port bit corresponding
to each port to "0" to program as an input port or set to "1" to program as an output port.
Determine the output state of an output port by setting the I/O port output data port. Set the output data bit corresponding
to each port to "1" to output the "H" level or set to "0" to output the "L" level.
I/O control data and I/O port output data are programmed and controlled at the OUT1 instruction data port-3, the OUT3
instruction.
When the IN3 instruction is executed, the pin state is read into the data memory. Note that execution of the IN3
instruction has no influence on the contents of the output latch.
OT1/OT2 output is programmed by the contents of the DO control port. (→ Refer to the section on Phase comparator.)
Note: There is no I/O control port for N-ch open-drain ports (I/O ports 6, 8 and 9-0). To set these ports as input
ports, set high impedance by specifying output data to "1".
Note: I/O port 1, I/O port 2, ... correspond to pin names P1-0 to P1-3, P2-0 to P2-3, ....
Note: The contents of output ports become unfixed after a system reset. It is recommended that the output
data be determined before output setting.
Note: Data select port increments by 1 automatically when φL10 to φL15, φK10 and φK11 on the I/O map are
accessed.
Note: The state of a pin that has been set to output is read when the IN3 instruction is executed.
Note: All the input circuits have the AND structure, which turns the AND gate on only when data reading (IN
instruction) is executed. There is little influence on consumption current; even when the input is in the
floating condition or has midpoint potential. This enables pull-up at a potential lower than the V
potential and output at three levels. Pay close attention to setting to the break pin, serial interface or
interrupt input, because the consumption current will increase rapidly when the input has midpoint
potential.
64
TC9349AFG
DD
2006-02-24

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