Table of Contents
Advertisement
2. Interrupt stack register (ISR)
The interrupt stack register (ISR) is a 14 bit × 16 page register. When interrupt processing is executed, the contents of the
26-bit G-register, data selection, carry flag, and data register are stored automatically. This register consists of four pages
and is specified with a two-bit interrupt stack pointer (ISP). When interrupt is generated, the G-register and other 26-bit
register contents are transmitted to the interrupt register. Simultaneously, the interrupt stack pointer is adjusted by -1. When
the RNI instruction is executed after the interrupt processing is finished, G-register and other 26-bit register contents are
returned and the interrupt stack pointer is increased by +1. In this way, the interrupt stack register (ISR) is used as a save
register for when interrupt occurs.
The Interrupt Stack register consists of four pages, and there are four interrupt stack levels.
The interrupt stack register and the interruption stack pointer are arranged on the I/O map, and their contents can be
referred to and rewritten.
φ L/K10(0)
Y1
Y2
Y4
Y8
ISP0
ISP1
*/0
*/0
Interrupt stack pointer
φ L/K10(8)
ISRG0 ISRG1 ISRG2 ISRG3
φ L/K10(9)
ISRG4
φ L/K10(A)
ISRS0 ISRS1 SEL4 ISRS2
φ L/K10(B)
ISRCA
φ L/K10(C)
ISRd0 ISRd1 ISRd2 ISRd3
φ L/K10(D)
ISRd4 ISRd5 ISRd6 ISRd7
φ L/K10(E)
ISRd8 ISRd9
φ L/K10(F)
ISRd1
Page 0
Page 1
Page 2
At the time of interruption processing execution
RNI instruction processing execution
Interrupt stack register
Y1
Y2
Y4
Y8
*/0
*/0
*/0
*/0
*/0
*/0
ISRd1
ISRd1
0
1
ISRd1
ISRd1
ISRd1
2
3
4
5
Page 3
46
(ISP) ← ISP+1
(ISP) ← ISP-1
Y1
φ L/K18
G0
φ L/K19
G4
At the time of interruption
processing execution
φ L/K1A
SEL1 SEL2 SEL4 SEL8
φ L/K1B
CA
φ L/K1C
d 0
φ L/K1D
d 4
φ L/K1E
d 8
RNI instruction
processing execution
φ L/K1F
d 12
TC9349AFG
Y2
Y4
Y8
G1
G2
G3
*/0
*/0
*/0
*/0
*/0
*/0
d 1
d 2
d3
d 5
d 6
d7
d 9
d 10
d11
d 13
d 14
d15
G-register
Data select
Carry flag
Data register
2006-02-24
Advertisement
Table of Contents
