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(2)
Interrupt latch
The interrupt latch is set to "1" through the issuing of an interrupt request from peripheral hardware. If interrupt is
enabled, an interrupt reception request will be sent to the CPU, which will execute the interrupt routine and carry out
branching. The data latch is automatically reset to "0" if an interrupt is received at this time. Interrupt latch data can
read by the program and the existence or nonexistence of an interrupt request can be determined on an individual
basis. An interrupt latch that has been set to "1" by interrupt request can also be reset to "0", and the interrupt request
can be canceled or initialized.
Y1
Y2
Y4
φL21
ILR1
ILR2
ILR3
Interrupt latch reset
Y1
Y2
Y4
φK21
IL1
IL2
IL3
Interrupt latch data
Note: Do not execute interrupt latch reset during interrupt processing.
(3)
Interrupt priority circuit block
The interrupt priority circuit is a circuit that determines the order in which interrupts are processed if interrupt
requests occur simultaneously or if interrupt is enabled after multiple interrupt requests have occurred. Vector
addresses to the interrupt routine are also generated by this block. The interrupt priority level can be set through
programming. The priority level is determined by setting the interrupt ID No. corresponding to each interrupts factor
to the interrupt priority level setting port. The interrupt priority level setting ports are composed of priority levels 1 to
4, and the circuit sets the interrupt ID No. in order of the priority levels 1 to 4. For instance, when the interrupt
priority level is set in the order of serial interface (2), INTR1 pin (0), INTR2 pin (1) and timer counter (3), then 2h, 0h,
1h, and 3h (φL14(6) = 2h, φL14(7) = dh) are set to priority levels 1 to 4. These ports can be accessed with an OUT1
instruction for which [CN = 4H] is specified in the operand and 6h and 7h are specified for the data selection ports
(φK/L1A).
Interrupt ID No.
0
1
2
Serial interface / timer port / decreased voltage detection
3
Y1
Y2
φL14(6)
PRI1-0 PRI1-1 PRI2-0 PRI2-1
Priority 1
Note: Do not set the same interrupt ID No. to each interrupt priority level.
Note: Do not change the interrupt priority setting during interrupt permission and interrupt processing.
Note: Interrupt priority after system reset reverts to an order corresponding to that of the interrupt ID No.'s
(i.e., ID No. 0 → Priority Level 1).
Y8
ILR4
If set to "1", the interrupt latch is reset to "0".
Y8
IL4
0: No interrupt
1: Interrupt
IL1･･･INTR1 pin
IL2･･･INTR2 pin
IL3･･･Serial interface / Timer port / Detected decrease voltage
IL4･･･8-bit timer counter
Interrupt Factor
INTR1 pin
INTR2 pin / timer port
Timer counter
Y4
Y8
φL14(7)
PRI3-0 PRI3-1 PRI4-0 PRI4-1
Priority 2
Interrupt priority setting port
49
Set to "1" on issuance of interrupt request and reset
to "0" on interrupt acceptance.
Y1
Y2
Y4
Y8
Priority 3
Priority 4
Interrupt ID No. is set.
TC9349AFG
Vector Address
0001H
0002H
0003H
0004H
2006-02-24
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