Toshiba TC9349AFG Manual page 16

6. G-register (G-REG)
The G-register is a 5-bit register used for addressing the row address (DR = 00H to 1FH) of the data memory's 512 words.
This register is located on the I/O map and accessed by input-and-output instruction. The 5-bit contents can be directly set
by execution of the STIG instruction. (Refer to Register Ports.)
The contents of this register are effective when the MVGD or MVGS instruction is executed, and are not affected
through execution of any other instructions. The contents of the G-register are evacuated to the interrupt stack register when
an interrupt request is generated, and returned to the G-register during execution of the RNI instruction. (Refer to Interrupt
Stack Register.)
7. Data Register (DATA REG)
The data register consists of 16 bits and loads 16 bits of data from any address in the program memory on execution of
the DAL instruction. This register is used as one of the ports. The contents of the register are loaded into the data memory in
4-bit units when the IN1 instruction among the I/O instructions is executed. (Refer to Register Ports.) The contents of data
register are evacuated to the interrupt stack register when an interrupt request is generated, and returned to the data register
during execution of the RNI instruction. (Refer to Interrupt Stack Register.)
8. DAL Address Register (AR)
The DAL address register consists of 14 bits. When the DALR instruction is executed, 16 bits of the data of the program
memory on the address specified by the DAL address register is loaded to the data register. The contents in the DAL address
register are automatically increased by one whenever the DALR instruction is executed.
The contents of the data register can be transferred to the DAL address register by execution of the MVAR instruction.
The DAL address register is located on the I/O map and accessed by input and output instructions.
(Refer to Register Ports.)
9. Carry Flag (Ca Flag)
The carry flag register is set when either Carry or Borrow is issued in the result of calculation instruction execution, and
is reset if neither of these is issued. The flag is located on the I/O map and can be accessed by the input and output
instructions. (Refer to Register Port.)
The contents of a carry flag are changed by execution of only the addition, subtraction, CLT, CLTC, SHRC or RORC
instruction and are not affected by execution of other instructions. The contents of carry flag are evacuated to the interrupt
stack register when an interrupt request is generated, and returned to the carry flag during execution of the RNI instruction.
(Refer to Stack Register.)
10. Interrupt Stack Register (ISR)
This register consists of 4 levels and 26 bits. When an interrupt occurs, the contents of the G-register (5 bits), data select
(4 bits), carry flag (1 bit) and data register (16 bits) are automatically evacuated to the interrupt stack register. After interrupt
processing has been completed, these contents are returned to each register by the RIN instruction. Four levels of stack and
nesting are allowed in the interrupt stack register. (Refer to Interrupt Stack Register.)
11. Judge Circuit (J)
This circuit judges the skip conditions when an instruction with the skip function is executed. The program counter is
increased by two when the skip conditions are satisfied, and the subsequent instruction is skipped. There are 15 instructions
with a wide variety of skip functions available. (Refer to the items marked with a "*" symbol in Instruction Function and
Operation Table.)
12. Interrupt Circuit
An interrupt circuit branches to the various vector addresses according to the demands from peripheral hardware and
performs different types of interrupt processing. (Refer to Interrupt Function.)
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TC9349AFG
2006-02-24