Table of Contents
Advertisement
Introduction
1.4.1 Normal Mode
As its name implies, Normal Mode is the mode in which the SoC is placed for normal oper-
ation. The system clock is generated from the PLL. In this mode, the JTAG interface is
active and accesses the boundary scan TAP Controller. This TAP Controller controls the
boundary scan cells that exist around the periphery of the device.
The LH75400/01/10/11 device JTAG ID Code is:
This JTAG ID Code is equivalent to 0x0754061.
1.4.2 PLL Bypass Mode
The SoC can be configured to bypass its internal PLL and operate with an external clock
source. In this mode:
• The PLL is placed in Bypass Mode
• The lock output from the PLL is forced HIGH
• XTALIN becomes the direct clock input to the RCPC, replacing the PLL output.
The system clock can be scaled down from divide by 30 to divide by 2.
During PLL Bypass Mode, the TEST2 pin must remain LOW until nPOR is asserted and
the operating mode is changed.
1.4.3 Embedded ICE Mode
In Embedded ICE Mode, the JTAG port accesses the TAP Controller in the ARM7 core
and the ARM7 core is placed in Debug Mode.
1.5 Power Supplies
The core logic requires a 1.8 V supply. 5 V-tolerant, 3.3 V I/Os, requiring a 3.3 V supply,
are employed. These devices are designed to require a single 3.3 V supply. A
3.3 V-to-1.8 V linear regulator is integrated into the chip to be used to generate the 1.8 V
needed by the core logic.
• Nine pairs of power pins (VDD and VSS) are dedicated to the 3.3 V supply.
• Two pairs of power pins are dedicated to the 1.8 V supply.
• One pair of power pins is dedicated to the analog circuitry of the A-to-D converter.
• One pair of power pins is dedicated to the PLL and crystal oscillators.
1-4
[31:28] Version (0x0)
[27:12] Part Number (0x0754)
[11:1] Manufacturer's ID (0x030)
[0] (0x1)
LH75400/01/10/11 (Preliminary) User's Guide
7/15/03
Advertisement
Table of Contents
