Operating Modes; Table 1-3. Device Operating Modes - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide
An APB bridge is used to provide access to the various APB peripherals:
• Analog-to-Digital Converter
• Controller Area Network (LH75401 and LH75400 only)
• Counter/Timers
• General Purpose Input/Output
• I/O Configuration
• Real Time Clock
• Reset, Clock, and Power Controller
• Synchronous Serial Port
• UARTs
• Watchdog Timer.
Generally, APB peripherals are serviced by the ARM core. This arrangement maximizes
system performance by allowing the DMA Controller to transfer data while the ARM core
executes from Tightly Coupled Memory (TCM).

1.4 Operating Modes

The SoCs support three operating modes:
• Normal Mode
• PLL Bypass Mode
• Embedded ICE Mode.
The operating mode that the SoC enters at Power-on Reset is determined by the state of
the TEST1, TEST2, and nRESETIN signals. Table 1-3 shows the signal states that corre-
spond to each operating mode.
The TEST1, TEST2, and nRESETIN signals are latched on the rising edge of nPOR. The
device remains in that operating mode until power is removed or nPOR transitions from
LOW to HIGH.

Table 1-3. Device Operating Modes

OPERATING MODE TEST2 TEST1 nRESETIN
Reserved
PLL Bypass
Reserved
Reserved
Embedded ICE
Normal
7/15/03
0 0 0
0 0 1
0 1 x
1 0 0
1 0 1
1 1 x
Introduction
1-3