LH75400/01/10/11 (Preliminary) User's Guide
20.3.2.32 Timer Interrupt Enable Register
Register Bank: 3
TMIE is the Timer Interrupt Enable Register for the timer block. The TMIE Register masks-
out interrupt requests generated by the status bits of the TMST Register.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:3
2
1
Table 20-73. TMIE Register
31
30
29
28
27
0
0
0
0
0
R
R
R
R
R
15
14
13
12
11
0
0
0
0
0
R
R
R
R
R
Table 20-74. TMIE Register Definitions
NAME
///
Reserved Do not modify. Read as zero.
TBIE
Timer A Expired Interrupt Enable Enables Interrupt on TAEx bit of TMST.
TAIE
Timer B Expired Interrupt Enable Enables Interrupt on TBEx bit of TMST.
26
25
24
23
22
///
0
0
0
0
0
R
R
R
R
R
10
9
8
7
6
///
0
0
0
0
0
R
R
R
R
R
0xFFFC2000 + 0x18
DESCRIPTION
6/17/03
UART2
21
20
19
18
17
0
0
0
0
0
R
R
R
R
R
5
4
3
2
1
TBIE TAIE
0
0
0
0
0
R
R
R
R
RW
16
0
R
0
0
RW
20-43