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UART2
20.3.3 UART2 Interrupts
There are two levels of interrupt/status reporting within UART2: block-level interrupts and
second-level interrupts.
• Block-level interrupts include Rx FIFO, Tx FIFO, receiver, transmitter, and timer inter-
rupts. The status of these blocks is reported in the General Status and General
Interrupt Registers.
• Second-level interrupts are those generated by the receiver and timers blocks.
Interrupt requests are maskable at both the block level and at the individual source level
within the module.
Each block has a fixed priority. If more than one unmasked block requests interrupt ser-
vice, the on-chip interrupt controller resolves the contention on a priority basis.
An interrupt request from a particular block is activated if one of the unmasked status bits
within the Status Register for the block is set. A CPU service operation, such as reading
the appropriate Status Register, resets the status bits.
20.3.3.1 Acknowledge Modes
The interrupt logic asserts an interrupt signal to the VIC when an interrupt is coded into the
General Interrupt Register.
UART2 has two Interrupt Acknowledgment Modes: Automatic Acknowledge and
Manual Acknowledge.
• An interrupt-service operation is considered an automatic acknowledgment in situations
where the ARM7TDMI-S core must issue an explicit interrupt acknowledge command
back to the UART2 peripheral. This causes the interrupt signal from UART2 to the VIC
to go inactive for two clock cycles. After two clock cycles elapse, UART2 determines
whether it should reassert the interrupt if there are other UART2 interrupts pending.
• In Manual Acknowledge Mode, the ARM7TDMI-S core must issue an explicit Interrupt
Acknowledge command via the Interrupt Acknowledge bit of the Internal Command
Register. As a result, the INT signal to the VIC is forced LOW for two clocks and
then updated.
NOTE: Do not use Automatic Acknowledge Mode. Use Manual Acknowledge Mode instead.
20-44
LH75400/01/10/11 (Preliminary) User's Guide
6/17/03
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