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Synchronous Serial Port
18.3.3 National Semiconductor Frame Format
Unlike the full-duplex transmission capabilities that the other two frame formats support,
the National Semiconductor Microwire format uses a special half-duplex, master-slave
messaging technique. In this mode:
1.
When a frame begins, an 8-bit control message is transmitted to the off-chip slave.
During this transmission, the SSP does not receive incoming data.
2.
After the message is sent, the off-chip slave decodes it, waits one serial clock after
the last bit of the 8-bit control message has been sent, and responds with the
requested data. The returned data can be 4 to 16 bits long, making the total frame
13 to 25 bits long.
During reception, data goes through a serial-to-parallel conversion before being placed
into the receive FIFO. The data is then read out via the AMBA APB interface.
Figure 18-9 shows the National Semiconductor Microwire format for a single transfer.
Figure 18-10 shows this format for continuous transfers.
18.4 Clock Generation
The serial bit rate is derived by dividing down the system clock, HCLK. The clock is first
divided by an even prescale value, CPSDVSR, from 2 to 254, which is programmed in the
CPSR Register. The clock is further divided by a value from 1 to 256, which is SCR + 1
(where SCR is the value programmed in the CTRL0 Register). The frequency of the output
clock SSPCLK is defined as ƒSSPCLK ÷ (CPSDVSR × (1 + SCR)).
18-8
LH75400/01/10/11 (Preliminary) User's Guide
6/17/03
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