Watchdog Timer
16.3.1.4 Counter Section 0 Register
CNT0 is the Counter Section 0 Register.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:8
7:0
16.3.1.5 Counter Section 1 Register
CNT1 is the Counter Section 1 Register.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:8
7:0
16-6
31
30
29
28
0
0
0
0
R
R
R
R
15
14
13
12
///
0
0
0
0
R
R
R
R
Table 16-9. CNT0 Register Definitions
NAME
///
Counter Sub-Section 0 Current Count Value Holds bits [7:0] of the current count value.
31
30
29
28
0
0
0
0
R
R
R
R
15
14
13
12
///
0
0
0
0
R
R
R
R
Table 16-11. CNT1 Register Definitions
NAME
///
Counter Sub-Section 1 Current Count Value Holds bits [15:8] of the current count value.
LH75400/01/10/11 (Preliminary) User's Guide
Table 16-8. CNT0 Register
27
26
25
24
23
///
0
0
0
0
0
R
R
R
R
R
11
10
9
8
7
0
0
0
0
0
R
R
R
R
R
0xFFFE3000 + 0x0C
Reserved Writing to these bits has no effect. Reading returns 0.
Table 16-10. CNT1 Register
27
26
25
24
23
///
0
0
0
0
0
R
R
R
R
R
11
10
9
8
7
0
0
0
0
0
R
R
R
R
R
0xFFFE3000 + 0x10
Reserved Writing to these bits has no effect. Reading returns 0.
6/17/03
22
21
20
19
0
0
0
0
R
R
R
R
6
5
4
3
Counter Sub-Section 0
0
0
0
0
R
R
R
R
DESCRIPTION
22
21
20
19
0
0
0
0
R
R
R
R
6
5
4
3
Counter Sub-Section 1
0
0
0
0
R
R
R
R
DESCRIPTION
18
17
16
0
0
0
R
R
R
2
1
0
0
0
0
R
R
R
18
17
16
0
0
0
R
R
R
2
1
0
0
0
0
R
R
R