Peripheral Clock Control Register 1; Table 9-20. Apbperiphclkctrl1 Register; Table 9-21. Apbperiphclkctrl1 Register Definitions - Sharp Blue Treak LH75400 User Manual

Reset, Clock, and Power Controller

9.3.2.9 Peripheral Clock Control Register 1

APBPeriphClkCtrl1 is the Peripheral Clock Control Register 1. This register controls the LCD
and SSP peripheral clocks. When writing to this register, setting a data bit to one stops the
clock of the corresponding peripheral. The active bits used in this register are Read/Write.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:16
15:9
9:2
1
0
9-14

Table 9-20. APBPeriphClkCtrl1 Register

31 30 29 28 27
0 0 0 0 0
R R R R R
15 14 13 12 11
///
1 1 1 1 1
R R R R R

Table 9-21. APBPeriphClkCtrl1 Register Definitions

FIELD NAME
/// Reserved Writing to these bits has no effect. Reading returns 0.
/// Reserved Read as 1.
/// Read as 1, always write 1 to these bits.
SSP Peripheral Clock
SSP
0 = Does not stop the SSP peripheral clock.
1 = Stops the SSP peripheral clock.
LCD Peripheral Clock
LCD
0 = Does not stop the LCD peripheral clock.
1 = Stops the LCD peripheral clock.
LH75400/01/10/11 (Preliminary) User's Guide
26 25 24 23 22
///
0 0 0 0
R R R R R
10 9 8 7
1 1 1 1
R RW RW RW RW
0xFFFE2000 + 0x28
DESCRIPTION
7/15/03
21 20 19 18
0 0 0 0 0
R R R R
6 5 4 3 2
///
1 1 1 1 1
RW RW RW RW
17 16
0 0
R R
1 0
SSP LCD
1 1
RW RW