Communication Using The Multiple Cpu High Speed Transmission Area And Auto Refresh - Mitsubishi Electric MELSEC Q Series User Manual

14.1.3
Communication using the multiple CPU high speed
transmission area and auto refresh
This is a communication method that uses the auto refresh area in the multiple CPU high speed transmission area in
the CPU shared memory.
Refresh is performed at certain intervals (multiple CPU high speed transmission cycle = 0.88ms).
Communication by the multiple CPU high speed transmission area is allowed when the following conditions are all satisfied.
• A multiple CPU high speed main base unit (Q3DB) is used.
• Any of universal model QCPUs (except for Q00UCPU, Q01UCPU, and Q02UCPU) and C Controller modules
(Q24DHCCPU-V, Q24DHCCPU-VG, Q12DCCPU-V (Basic mode), or Q12DCCPU-V (Extended mode)) is No.1.
• Any two of universal model QCPUs (except for Q00UCPU, Q01UCPU, and Q02UCPU), C Controller modules
(Q24DHCCPU-V, Q24DHCCPU-VG, Q12DCCPU-V (Basic mode), or Q12DCCPU-V (Extended mode)), or Motion
CPUs (Q172DCPU (-S1), Q173DCPU (-S1), Q172DSCPU, or Q173DSCPU) are used.
(1) Processing overview
Operations outline of auto refresh in a configuration in which an universal model QCPU and a C Controller
module are used as No.1 and No.2 modules, respectively is illustrated below.
Universal model QCPU (CPU No.1)
Processing Processing in universal model QCPU (No.1)
In END processing by the No.1 module, device data of
1) the No.1 module are transferred to the auto refresh area
of the host station.
The multiple CPU high speed transmission area data in
2)
the No.1 module are transmitted to the No.2 module.
3)
4)
5)
In END processing by the No.1 module, the received
6)
data are transferred to the No.2 module's device data.
CPU shared memory
CPU No.1 multiple CPU high speed
transmission area
Auto refresh area
CPU No.2 multiple CPU high speed
transmission area
Auto refresh area
1)
6)
Device
For Universal model QCPU (CPU No.1)
For C Controller module (CPU No.2)
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CHAPTER 14 FUNCTIONS USED BY MULTIPLE CPU SYSTEM
Q24DHC-V Q24DHC-VG
C Controller module (CPU No.2)
CPU shared memory
CPU No.1 multiple CPU high speed
2)
transmission area
Auto refresh area
CPU No.2 multiple CPU high speed
5)
transmission area
Auto refresh area
User program
QBF_FromBuf function (read) data
QBF_ToBuf function (write) data
Processing in C Controller module (No.2)
The No.2 module's user program reads the received data
by executing the bus interface function (QBF_FromBuf).
The No.2 module's user program write data into the auto
refresh data area by executing the bus interface function
(QBF_ToBuf).
The multiple CPU high speed transmission area data in the
No.2 module are transferred to the No.1 module.
Q24DHC-LS Q26DHC-LS Q12DC-V
4)
3)
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