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CONTROL REGISTERS
WTCON
— Watch Timer Control Register
Bit Identifier
RESET Value
RESET
Read/Write
Addressing Mode
.7
.6
.5–.4
.3–.2
.1
.0
NOTE: Watch timer clock frequency(fw) is assumed to be 32768Hz.
4-44
.7
.6
0
0
R/W
R/W
Register addressing mode only
Watch Timer Clock Selection Bit
0
Main system clock divided by 2
1
Sub system clock (fxt)
Watch Timer Interrupt Enable Bit
0
Disable watch timer interrupt
1
Enable watch timer interrupt
Buzzer Signal Selection Bits
0
0
0.5 kHz buzzer (BUZ) signal output
0
1
1 kHz buzzer (BUZ) signal output
1
0
2 kHz buzzer (BUZ) signal output
1
1
4 kHz buzzer (BUZ) signal output
Watch Timer Speed Selection Bits
0
0
0.5 s Interval
0
1
0.25 s Interval
1
0
0.125 s Interval
1
1
1.955 ms Interval
Watch Timer Enable Bit
0
Disable watch timer; Clear frequency dividing circuits
1
Enable watch timer
Watch Timer Interrupt Pending Bit
0
Interrupt is not pending, clear pending bit when write
1
Interrupt is pending
S3C8248/C8245/P8245/C8247/C8249/P8249
.5
.4
0
0
R/W
R/W
R/W
7
(fxx/128)
FAH
Set 1, Bank 1
.3
.2
.1
0
0
0
R/W
R/W
.0
0
R/W
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