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ELECTRICAL DATA
°
°
(T
= -40
C to +85
C, V
A
Oscillator
Crystal
Ceramic
External clock
RC
°
°
(T
= -40
C to +85
C, V
A
Oscillator
V
Crystal
DD
Stabilization occurs when V
Ceramic
oscillator voltage range.
External clock
X
IN
NOTE: Oscillation stabilization time (t ST1 ) is the time required for the CPU clock to return to its normal oscillation
frequency after a power-on occurs, or when Stop mode is ended by a RESET signal.
The RESET should therefore be held at low level until the t ST1 time has elapsed
19-12
Table 19-11. Main Oscillator Frequency (f
= 1.8 V to 5.5 V)
DD
Clock Circuit
X
X
IN
OUT
C1
C2
X
X
IN
OUT
C1
C2
X
X
IN
OUT
X
X
IN
OUT
R
Table 19-12. Main Oscillator Clock Stabilization Time (t
= 4.5 V to 5.5 V)
DD
Test Condition
= 4.5 V to 5.5 V
input high and low level width (t
Test Condition
Crystal oscillation frequency
Ceramic oscillation
frequency
X
input frequency
IN
V
= 5 V
DD
is equal to the minimum
DD
, t
)
XH
XL
S3C8248/C8245/P8245/C8247/C8249/P8249
)
OSC1
Min
Typ
1
–
1
–
1
–
1
–
)
ST1
Min
Typ
–
–
–
–
50
–
Max
Unit
10
MHz
10
MHz
10
MHz
2
MHz
Max
Unit
10
ms
4
ms
500
ns
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