Advertisement
S3C8248/C8245/P8245/C8247/C8249/P8249
Timer 1 Counter High-Byte Register
(T1CNTH) FCH, Set 1, Bank 1, R
MSB
.7
.6
.5
Timer 1 Counter Low-Byte Register
(T1CNTL) FDH, Set 1, Bank 1, R
MSB
.7
.6
.5
Timer 1 Data High-Byte Register
(T1DATAH) FEH, Set 1, Bank 1, R/W
MSB
.7
.6
.5
Timer 1 Data Low-Byte Register
(T1DATAL) FFH, Set 1, Bank 1, R/W
MSB
.7
.6
.5
NOTE:
Pending bit is located in INTPND (D2H, set1) register.
Figure 12-7. Timer 1 Control Register (T1CNTH/L)
.4
.3
.2
.1
Reset Value: 00H
.4
.3
.2
.1
Reset Value: 00H
.4
.3
.2
.1
Reset Value: FFh
.4
.3
.2
.1
Reset Value: FFh
16-BIT TIMER 0/1
.0
LSB
.0
LSB
.0
LSB
.0
LSB
12-9
Advertisement
