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Samsung S3C8248 User Manual page 135

8-bit cmos

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INSTRUCTION SET
CLR
— Clear
CLR
dst
dst ← "0"
Operation:
The destination location is cleared to "0".
Flags:
No flags are affected.
Format:
opc
Examples:
Given: Register 00H = 4FH, register 01H = 02H, and register 02H = 5EH:
CLR
CLR
In Register (R) addressing mode, the statement "CLR 00H" clears the destination register 00H
value to 00H. In the second example, the statement "CLR @01H" uses Indirect Register (IR)
addressing mode to clear the 02H register value to 00H.
6-28
dst
00H
Register 00H = 00H
@01H →
Register 01H = 02H, register 02H = 00H
S3C8248/C8245/P8245/C8247/C8249/P8249
Bytes
Cycles
Opcode
2
4
4
Addr Mode
(Hex)
dst
B0
R
B1
IR

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