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Samsung S3C8248 User Manual page 46

8-bit cmos

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S3C8248/C8245/P8245/C8247/C8249/P8249
4
CONTROL REGISTERS
OVERVIEW
In this chapter, detailed descriptions of the S3C8248/C8245/C8247/C8249 control registers are presented in an
easy-to-read format. You can use this chapter as a quick-reference source when writing application programs.
Figure 4-1 illustrates the important features of the standard register description format.
Control register descriptions are arranged in alphabetical order according to register mnemonic. More detailed
information about control registers is presented in the context of the specific peripheral hardware descriptions in
Part II of this manual.
Data and counter registers are not described in detail in this reference chapter. More information about all of the
registers used by a specific peripheral is presented in the corresponding peripheral descriptions in Part II of this
manual.
The locations and read/write characteristics of all mapped registers in the S3C8248/C8245/C8247/C8249 register
file are listed in Table 4-1. The hardware reset value for each mapped register is described in Chapter 8, "RESET
and Power-Down."
Register Name
LCD control register
LCD mode register
Interrupt pending register
Basic timer control register
Clock control register
System flags register
Register pointer 0
Register pointer 1
Stack pointer (high byte)
Stack pointer (low byte)
Instruction pointer (high byte)
Instruction pointer (low byte)
Interrupt request register
Interrupt mask register
System mode register
Register page pointer
Table 4-1. Set 1 Registers
Mnemonic
LCON
LMOD
INTPND
BTCON
CLKCON
FLAGS
RP0
RP1
SPH
SPL
IPH
IPL
IRQ
IMR
SYM
PP
Decimal
Hex
208
D0H
209
D1H
210
D2H
211
D3H
212
D4H
213
D5H
214
D6H
215
D7H
216
D8H
217
D9H
218
DAH
219
DBH
220
DCH
221
DDH
222
DEH
223
DFH
CONTROL REGISTER
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
4-1

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