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16-BIT TIMER 0/1
TIMER 0 CONTROL REGISTER (T0CON)
You use the timer 0 control register, T0CON, to
— Enable the timer 0 operating (interval timer)
— Select the timer 0 input clock frequency
— Clear the timer 0 counter, T0CNT
— Enable the timer 0 interrupt and clear timer 0 interrupt pending condition
T0CON is located in set 1, at address F1H, and is read/write addressable using register addressing mode.
A reset clears T0CON to "00H". This sets timer 0 to disable interval timer mode, selects the TBOF, and disables
timer 0 interrupt. You can clear the timer 0 counter at any time during normal operation by writing a "1" to
T0CON.3
To enable the timer 0 interrupt (IRQ2, vector E6H), you must write T0CON.2, and T0CON.1 to "1". To generate
the exact time interval, you should write T0CON.3 and 0, which cleared counter and interrupt pending bit. To
detect an interrupt pending condition when T0INT is disabled, the application program polls pending bit,
T0CON.0. When a "1" is detected, a timer 0 interrupt is pending. When the T0INT sub-routine has been serviced,
the pending condition must be cleared by software by writing a "0" to the timer 0 interrupt pending bit, T0CON.0.
MSB
Timer 0 input clock selection bits:
000 = TBOF
010 = f
/256
XX
100 = f
/64
XX
110 = f
/8
XX
1 = f
XX
XX
12-2
Timer 0 Control Registers
F1H, Set 1, Bank 1, R/W, RESET; 00H
.7
.6
.5
Not used
Timer 0 counter clear bit:
0 = No affect
1 = Clear the timer 0 counter (when write)
NOTE:
For normal operation T0CON.3 bit must be set 1.
Figure 12-1. Timer 0 Control Register (T0CON)
.4
.3
.2
.1
Timer 0 interrupt enable bit:
0 = Disable interrupt
1 = Enable interrupt
Timer 0 count enable bit:
0 = Disable counting operation
1 = Enable counting operation
S3C8248/C8245/P8245/C8247/C8249/P8249
.0
LSB
Timer 0 interrupt pending bit:
0 = No interrupt pending
0 = Clear pending bit (when write)
1 = Interrupt is pending
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