Vi-2-14. Fdd Interface Circuit - Canon A-200 series Service Manual

VI-2-14. FDD Interface Circuit
For simplicity we have divided this paragraph into the following five sections:
* FDD Control Register
* Clock Generator Circuit
* FDC
*
Pre-Compensation Circuit
* Data Separation Circuit
• FOO
Control Register
This register selects the FDD unit A or B, resets the FDC and defines whether it permits an inter ­
ruption of the FDC or DMA request or not. It consists of 4-bit flip-flop circuits.
Descriptions for each bit are mentioned in Table 6-9.
110
Address Bit Description
3FO 2 FDC is reset when this bit is LOW.
3 H level of this bit allows FDC interruption and DMA
request.
4 L level of this bit selects Drive A
5 L level of this bit selects Drive B
Table 6-9
Figure 6-23 shows operations of the FDD Control Register.
Data transfer between the FDD and memory is made through the DMAC and FOC.
The FDC sends the DREQ signal to the DMAC when data transfer to/from the FOO becomes
enable. This signal is delayed for the time equivalent to four 2MHz clock cycles (2 micro seconds)
and then sent to the DREQ2 terminal of the DMAC after it is ANDed with the bit 3 of the FOD
control register.
When the OMAC receives the DMA request, it makes the CPU wait, and then sends the OACK2
signal to the FOC to begin the DMA transferring. When one block of data transfer is completed,
the FOC sends an interruption signal through the IRQ6 terminal of the PIe.
• Clock Generator Circuit
This circuit emits 16MHz, 8MHz and 2MHz clock signals used for the FDO interface circuit.
The 16MHz-clock is used as a fundamental clock for U104 (SED9420COB) and as a clock input
for the counter IC, U95.
Further, U104 emits 4MHz of clock signal by dividing the fundamental clock by four and then
supplies it to the FDC.
U95 generates 8MHz and 2MHz clock signals by dividing it by two and eight.
• FOC
This circuit employs the IC ",PD765AC. Followings are descriptions for each pin of this Ie.
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