Canon A-200 series Service Manual page 59

• PaJity Checking
RAMs have 1 bit of parity bits corresponding to everyone byte of even addresses and odd ad­
dresses. Parity bits are generated by U30 for even addresses and by U41 for odd addresses.
These ICs generates an even parity and odd parity according to 9-bit data input to the A through
I terminals. When writing data into RAM, their I terminals become LOW with the MRD signal out­
put from U77, and then U30 and U41 input data (MOO through MD7 for even addresses, M08
through MD15 for odd addresses) to their A through H terminals, and finally gets respective even
parities (MDEIP, MDOIP) before writing data to RAMs.
When reading, U30 and U41 input data (MOO through MD7 for odd addresses and M08 through
MD15 for even addresses) read from RAMs into their A through H terminals, and input the parity
bit (MDEOP for even address and MDOOP for odd address) into I terminal to ensure that read
data is valid.
If anyone bit is missing in reading, Sigma-ODD terminal of U30 or U41 becomes HIGH. This
signal makes to send Non Maskable Interrupt signal to the CPU at the rising edge of the MRD-N
signal after it has been ANDed with the AO or BHE signal.
o l - + - - - - - - P C 7
N D P I > - - - - - - - - - Q
NMI
EXPER > - - - - - - - '
N M I E N > - - - - - - . . . . . J
Figure 6-10
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