Vi-2-3. Nmi And Int Control Circuit - Canon A-200 series Service Manual

VI-2-3. NMI and INT Control Circuit
The 8086 has two interrupt terminals. One is the NMI (Non-maskable Interrupt) and the other
is the INT (Interrupt).
In the A-200, the NMI terminal is used to detect parity error at the main RAM, parity error from
the option slots and interrupt from the N DC.
The PIC sends the INT signal to the CPU after priority is given to one of the interrupt signals
from the internal or external devices.
Figure 6-6 shows the interrupt control circuit and Table 6-1 shows the assignment of IROO through
IRO? signals.
Priority Signal Description
High IROO
Interrupt from the timer IC (8253)
IR01 Interrupt from the keyboard
IR02 Interrupt from the optional slot
IR03 Interrupt from the optional slot
IR04 Interrupt from the USART (8250)
IR05
Interrupt from the optional slot
IR06
Interrupt from the FDC (J,tPD?65)
Low
IRO? Interrupt from the printer interface
Table 6-1
As Figure 6-6 shows, the NMI signal is ANDed with the NMIEN signal before it is sent to the
CPU. This NMIEN signal is the output of the register which is assigned with the I/O address OAXH
'from the CPU. The NMIEN signal is reset when the power for the computer is turned on, and
when the RAM checking involved in the initial power-on diagnostic program is completed, this
signal is set.
When the CPU receives this interruption, an execution jumps to the service routine having the
entry address of 0008H.
When the CPU is interrupted at the INT terminal, it returns the INTA (Interrupt Acknowledge) sig ­
nal to the PIC through the command bus. Then the PIC sends the vector address correspond­
ing to the preassigned interrupted device to the CPU through the data bus.
1D7
NMIC
'---<RESET
NMIr-----~7~7
==-___--,
INPER
'---P--RAM
CPU
PIC
IRQ7 i - - - - - M R D N
I N T i - - - - - ­ INT - l
IR06
IA05
IAQ4
IRQ3
PB4
I > - - - - - - - - - E X P E R
P - - - - - - - - - N D P I
BCU IRQ2
IRl
IROl
lOR
IROO
lOW
t-s
PiC
Data Bus 100-7
Figure 6-6
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