T3
T4
T1
T2
T3
Tw
Tw
Tw
Tw
Tw
Tw
T4
CPU·ClK
JI
II
II
II
II
II
II
II
II
II
II
!I~
___
(ClK)
DMA·ClK
(DClK)
SO- S2
HRQ
~
(DMAC)
___--1,
DMA·GO
HOLDA
(DMAC)
- - - _
...
_ - - _
....
_ - _
....
-
- - _
....
_--_
...
- - - -
- - - - - - - ,
AEN
AEN
(BCU, CEN)
m
RDY1
~
DMA-ADDR
DACK
MRD, MWR'
__
---'r---------~---------------------------------------~
~
lOR, lOW
(BCU)
MRD, lOR
----------------------------~,-
-.~~
__________________________Jl------'----------------------------------
(DMAC)
lOW,
MWR
______________________________
~r__
---~
I
-~~-----------------------------------
(DMAC)
DMA-RDY
(DMAC)
DMA CYCLE
Figure 6-14