Vi-2-5. Memory - Canon A-200 series Service Manual

VI-2-5. Memory
On the main P.C.B. of the A-200, 256K bytes of D-RAMs and 16K bytes of ROMs are installed.
In this section, we will describe on the addressing for ROM and RAM, and on how to check
parity bit of RAM.
• ROM addressing
The ROM signal output from the gate logic constructed with U85, U91 and U98 becomes LOW
when the CPU accesses the memory area higher than FCOOOH. Next, this signal is ANDed with
the BHE signal or AO signal.
When the CPU executes a byte transfer operation to the even addresses over FCOOOH, the AO
signal becomes LOW and the BHE signal becomes HIGH, and finally, ROMEV signal will be
output. Conversely, when the CPU executes a byte transfer operation to the odd addresses, the
AO becomes HIGH, the BHE becomes LOW and then the ROMOD signal will be output.
When the CPU executes a word transfer operation to the even addresses, the AO becomes LOW,
the BHE also becomes LOW and as a result, both the ROMEV and ROMOD signals are output.
When the ROMEV is LOW, the CPU selects the ROM U53, and when the ROMOD is LOW, selects
U62.
ROM
A19
A
18
">-----1'-.....
L..------r-"_ _
A 17
~----'_.J'
_.I~MDO-7
A16
A15
A 1 4 ~----1,---'"
AO>---------~~
~MD8-15
BHE
>---------~~~
MR-D-N
> - - - - - - - - - - - - - - - * - - d O E
Figure 6-8
• RAM Addressing
The 36 D-RAMs installed in the A-200 are categorized into following four groups.
*
OOOOOH through 1FFFEH having even addresses
* 00001 H through 1 FFFFH having odd addresses
*
20000H through 3FFFEH having even addresses
*
20001H through 3FFFFH having odd addresses
One of above four groups is selected by RAMLE (RAM Low Even), RAMLO (RAM Low Odd),
RAMHE (RAM High Even) and RAMHO (RAM High Odd) signals. For example, in the case of
transferring 1-byte data from the address OOOOH, the RAML signal from the YO terminal of U86
becomes LOW. Then this RAML signal is ANDed with the AO signal at U90 and further ANOed
with the MRD or MWR signal at the U85, and finally the RAMLE signal becomes Law.
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