Canon A-200 series Service Manual page 64

The pins ADO through A015 of the CPU are the time multiplexed address and data bus. U52
and U44 separates the contents of the address bus using the ALE signal that is obtained by
encoding the status signals SO through S2 from the CPU at the BCU.
Similarly, signals A16 through A19 are generated from A16/S3 through A19/S6 signals respective­
ly with U45 by using the ALE signal.
Among above 20-address signals, only lowest bit AO (CPU) signal is used with the BHE (CPU)
signal to determine whether lower 8 bits (DO - 07) or upper 8 bits (08 - 015) are accessed.
If an optional board which has 8-bit bus construction is used, this AO (CPU) signal is also used
by the bus control circuit to generate odd addresses when it executes a word transfer (2 bytes)
beginning from even addresses. That is, the bus control circuit makes the lowest bit AO to LOW
first, and then data in even addresses are transferred to the lower 8 bits in the data bus, and
makes the CPU to WAIT state. Finally, the AO becomes HIGH and then data in odd addresses
are transferred to the upper 8 bits in the data bus.
Thus, the lowest address line bit AO(CPU) signal and BHE(CPU) signal that gives a permission
to use the upper 8 bits of the data bus are not sent to the memory or I/O devices directly.
They are converted to the AO and BHE signals respectively according to current transfer modes,
and then they are sent to memory or I/O devices.
ADO through A015 are connected to the data bus through bi-directional buffers U57 and U58.
The chip enable terminals and the direction terminals of these ICs are connected to the DEN
and the
T/R
terminals of the BCU. Therefore, when the CPU assigns the AO through A15 as data
bus, these buffers become enable.
When accessing on-board RAM or ROM, data bus is connected to these memories through U35
and U46. The reason of this is as follows; since RAMs and ROMs mounted on the main board
have 16-bit bus construction, one byte data in even address is transferred to DO through 07, one
byte data in odd address is transferred to 08 through 015 respectively, data begins from even
address is transferred to DO through 07 and data begins from odd address is transferred to 08
through 015 when in one word (2 bytes) transfer mode. If RAMs or V-RAMs mounted on an op­
tional board have 16-bit data bus construction, they are connected to the data bus through U68
and U65.
Another two latches and buffers are effective only for memory or I/O devices having 8-bit data
bus construction. Usually, one of two latches works in read operation and one of two buffers
works in write operation during the CPU cycle. The combination for using these gates
depends on four factors - accessing from the CPU, accessing from the DMAC, even ad­
dress and odd address. Detail of their combination are indicated in Table 6-3.
The command bus consists of MRD, MWR, lOR, lOW, DEN,
T/R,
and ALE signals. The BCU
generates these signals using the status signals SO through S3 from the CPU and AEN, CEN
and INTA signals from the I/O devices. These signals are used by the CPU when it accesses
memory or I/o. However, when the DMAC accesses memory or I/O without CPU's intervention,
it generates peculiar MRO, MWR, lOR and lOW signals.
Table 6-4 describes about the signals in command bus.
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