Fujitsu 8FX Hardware Manual page 69

MB95630H Series
Table 3.5-2 Table of State Transition with Deep Standby Mode Enabled (Transition to and from
Standby Mode)
State transition
Normal operation after reset
<1>
state
(1)
Sleep mode
(2)
(3)
Stop mode
(4)
(5)
Time-base timer mode
(6)
(7)
Watch mode
(8)
MN702-00009-2v0-E
After a reset, the device transits to main CR clock mode.
If the reset that has occurred is a power-on reset, a watchdog reset, a software reset,
or an external reset, the device always wait for the main CR clock oscillation
stabilization wait time and the sub-CR clock oscillation stabilization wait time to
elapse.
The device transits to sleep mode when "1" is written to the sleep bit in the standby
control register (STBC:SLP).
In response to an interrupt from a peripheral function, after the Flash recovery wait
time elapses, the device returns to the RUN state.
During the Flash recovery wait time, the device transits to sleep mode. (The CPU
stops its operation; the peripheral function resumes its operation.)
However, if a program is being executed on the RAM, no Flash recovery wait time
occurs.
The device transits to stop mode when "1" is written to the stop bit in the standby
control register (STBC:STP).
In response to an external interrupt, after the oscillation stabilization wait time
required according to the current clock mode and the Flash recovery wait time elapse,
the device returns to the RUN state.
When the oscillation stabilization wait time is shorter than the Flash recovery wait
time, after the oscillation stabilization wait time elapses, the device transits to sleep
mode and remains in sleep mode until the Flash recovery wait time elapses.
When the oscillation stabilization wait time is longer than the Flash recovery wait
time, after the oscillation stabilization wait time elapses, the device returns to the
RUN state.
However, if a program is being executed on the RAM, no Flash recovery wait time
occurs.
The device transits to time-base timer mode when "1" is written to the watch bit in
the standby control register (STBC:TMD) in main clock mode or main CR clock
mode.
In response to an interrupt from a peripheral function, after the Flash recovery wait
time elapses, the device returns to the RUN state.
During the Flash recovery wait time, the device transits to sleep mode. (The CPU
stops its operation; the peripheral function resumes its operation.)
However, if a program is being executed on the RAM, no Flash recovery wait time
occurs.
The device transits to watch mode when "1" is written to the watch bit in the standby
control register (STBC:TMD) in subclock mode or sub-CR clock mode.
In response to an interrupt from a peripheral function, after the Flash recovery wait
time elapses, the device returns to the RUN state.
During the Flash recovery wait time, the device transits to sleep mode. (The CPU
stops its operation; the peripheral function resumes its operation.)
However, if a program is being executed on the RAM, no Flash recovery wait time
occurs.
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 3 CLOCK CONTROLLER
3.5 Operations in Low Power Consumption
Mode (Standby Mode)
Description
47