Fujitsu 8FX Hardware Manual page 39

MB95630H Series
■ Block Diagram of Clock Controller
Figure 3.1-1 is the block diagram of the clock controller.
System clock control register 2 (SYCC2)
SRDY MRDY SCRDY MCRDY
Main CR
(5)
clock oscillator
circuit
Sub-CR
clock oscillator
circuit
Main clock
(1)
oscillator
circuit
Subclock
(2)
oscillator
circuit
Oscillation
stabilization
wait circuit
MPEN MPMC1 MPMC0 MPRDY
PLL control register (PLLC)
SWT3 SWT2 SWT1 SWT0
Oscillation stabilization wait time setting register (WATR)
(1): Main clock (F
(2): Subclock (F
(3): Main clock
(4): Subclock
MN702-00009-2v0-E
Figure 3.1-1 Block Diagram of Clock Controller
SOSCE MOSCE SCRE MCRE
(6)
Divide by 2
(3)
Divide by 2
(4)
Divide by 2
Main CR PLL
(9)
clock oscillator
circuit
- - -
MWT3 MWT2 MWT1 MWT0
) (5): Main CR clock (F
CH
) (6): Sub-CR clock (F
CL
(7): Source clock (SCLK)
(8): Machine clock (MCLK)
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 3 CLOCK CONTROLLER
Standby control register 2 (STBC2)
- - - -
Standby control register (STBC)
STP SLP SPL SRST
System clock selector
Prescaler
(7)
No division
Divide by 4
(8)
Divide by 8
Divide by 16
Source clock
selection
control circuit
-
SCM2 SCM1 SCM0 SCS2
System clock control register (SYCC)
) (9): Main CR PLL clock (F
CRH
)
CRL
3.1 Overview
- - -
DSTBYX
To Flash memory
TMD - - -
Watch or time-base
timer mode
Sleep mode
Stop mode
Clock Supply to CPU
control
Supply to perip-
circuit
heral resources
Clock for time-base timer
Clock for watch timer
SCS1 SCS0 DIV1 DIV0
)
MCRPLL
17