Fujitsu 8FX Hardware Manual page 319

MB95630H Series
■ Sample Operation Flow Chart of Clock Supervisor
Figure 17.3-6 Sample Operation Flow Chart of Clock Supervisor
Clock supervision starts
Oscillation stabilization
wait time elapses
YES
Read the main clock /
subclock oscillation
stabilization bit*
"1"
Set CMCSEL,
TBTSEL[2:0]
and CMCEN
Read CMCEN
"0"
CMDR value =
estimate ?
YES
Change target external clock
(Normal oscillation)
*: Main clock oscillation stabilization bit — SYCC2:MRDY
Subclock oscillation stabilization bit — SYCC2:SRDY
MN702-00009-2v0-E
CHAPTER 17 CLOCK SUPERVISOR COUNTER
NO
In main CR clock mode, wait for the elapse of the
specified main clock/subclock oscillation stabilization
wait time by using the time-base timer interrupt or
other methods.
"0"
"1"
NO
Keep main CR clock mode
(The external clock is
oscillating at an abnormal
frequency.)
FUJITSU SEMICONDUCTOR LIMITED
17.3 Operations
Keep main CR clock mode
(If the oscillation stabilization wait
time has elapsed but the main
clock/subclock oscillation stabili-
zation bit* is not set to "1", that
means the external clock is dead
or the external clock frequency is
abnormal.)
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