Pll Control Register (Pllc) - Fujitsu 8FX Hardware Manual

MB95630H Series
3.3.2

PLL Control Register (PLLC)

The PLL control register (PLLC) controls the main CR PLL clock multiplication
rate settings.
■ Register Configuration
bit 7
Field MPEN
Attribute R/W
Initial value 0
■ Register Functions
[bit7] MPEN: Main CR PLL clock enable bit
This bit enables or disables the main CR PLL clock.
When SCS[2:0] are set to "0b111", this bit is automatically set to "1".
When SCS[2:0] or SCM[2:0] are set to "0b111", writing "0" to this bit has no effect on operation.
This bit is automatically set to "0" when the clock mode transits from one mode to another mode except main
CR PLL clock mode.
When the current clock mode is subclock mode or sub-CR clock mode, writing "1" to this bit has no effect on
operation.
bit7
Writing "0"
Writing "1"
[bit6:5] MPMC[1:0]: Main CR PLL clock multiplication rate select bits
These bits select a main CR PLL clock multiplication rate.
The settings of these bits can be modified only when the main CR PLL clock is stopped. Thus these bits can
be modified in main clock mode, main CR clock mode, subclock mode or sub-CR clock mode.
bit6:5
Writing "00"
Writing "01"
Writing "10"
Writing "11"
Note: When SCS[2:0] or SCM[2:0] are set to "0b111", writing values to MPMC[1:0] is prohibited.
[bit4] MPRDY: Main CR PLL clock oscillation stabilization bit
This bit indicates whether the main CR PLL clock oscillation is ready.
bit4
Reading "0"
Reading "1"
[bit3:0] Undefined bits
Their read values are always "0". Writing values to these bits has no effect on operation.
MN702-00009-2v0-E
6 5
MPMC1 MPMC0
R/W R/W
0 0
Disables the main CR PLL clock.
Enables the main CR PLL clock.
Main CR clock 2
Main CR clock 2.5
Main CR clock 3
Main CR clock 4
Indicates that main CR PLL clock is in the oscillation stabilization wait state or that the main CR
PLL clock oscillation has stopped.
Indicates that the main CR PLL clock oscillation wait time is over.
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 3 CLOCK CONTROLLER
4 3
MPRDY —
R —
X 0
Details
Details
Details
3.3 Registers
2 1
— —
— —
0 0
0
—
—
0
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