Philips LPC2194 User Manual page 203

Philips Semiconductors Preliminary User Manual
ARM-based Microcontroller LPC2119/2129/2292/2294
Sleep Mode
The CAN Controller will enter sleep mode if the SM bit in the CAN Mode register is 1, no CAN interrupt is pending, and there is
no activity on the CAN bus. Software can only set SM when RM in the CAN Mode register is 0; it can also set the WUIE bit in
the CAN Interrupt Enable register to enable an interrupt on any wake-up condition.
The CAN Controller wakes up (and sets WUI in the CAN Interrupt register if WUIE in the CAN Interrupt Enable register is 1) in
response to a) a dominant bit on the CAN bus, or b) software clearing SM in the CAN Mode register. A sleeping CAN Controller,
that wakes up in response to bus activity, is not able to receive an initial message, until after it detects Bus_Free (11 consecutive
recessive bits). If an interrupt is pending or the CAN bus is active when software sets SM, the wakeup is immediate.
Interrupts
Each CAN Controller produces 3 interrupt requests, Receive, Transmit, and "other status". The Transmit interrupt is the OR of
the Transmit interrupts from the three Tx Buffers. Each Receive and Transmit interrupt request from each controller is assigned
its own channel in the Vectored Interrupt Controller (VIC), and can have its own interrupt service routine. The "other status"
interrupts from all of the CAN controllers, and the Acceptance Filter LUTerr condition, are ORed into one VIC channel.
Transmit Priority
If the TPM bit in the CANMOD register is 0, multiple enabled Tx Buffers contend for the right to send their messages based on
the value of their CAN Identifier (TID). If TPM is 1, they contend based on the PRIO fields in bits 7:0 of their CANTFS registers.
In both cases the smallest binary value has priority. If two (or three) transmit-enabled buffers have the same smallest value, the
lowest-numbered buffer sends first.
The CAN controller selects among multiple enabled Tx Buffers dynamically, just before it sends each message.
CAN Controllers and Acceptance Filter 203 May 03, 2004