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Philips Semiconductors
ARM-based Microcontroller
Prescale Counter Register (PC: TIMER0 - T0PC: 0xE0004010; TIMER1 - T1PC: 0xE0008010)
The 32-bit Prescale Counter controls division of pclk by some constant value before it is applied to the Timer Counter. This allows
control of the relationship of the resolution of the timer versus the maximum time before the timer overflows. The Prescale
Counter is incremented on every pclk. When it reaches the value stored in the Prescale Register, the Timer Counter is
incremented and the Prescale Counter is reset on the next pclk. This causes the TC to increment on every pclk when PR = 0,
every 2 pclks when PR = 1, etc.
Match Registers (MR0 - MR3)
The Match register values are continuously compared to the Timer Counter value. When the two values are equal, actions can
be triggered automatically. The action possibilities are to generate an interrupt, reset the Timer Counter, or stop the timer. Actions
are controlled by the settings in the MCR register.
Match Control Register (MCR: TIMER0 - T0MCR: 0xE0004014; TIMER1 - T1MCR: 0xE0008014)
The Match Control Register is used to control what operations are performed when one of the Match Registers matches the Timer
Counter. The function of each of the bits is shown in Table 160.
Table 160: Match Control Register (MCR: TIMER0 - T0MCR: 0xE0004014; TIMER1 - T1MCR: 0xE0008014)
MCR
Function
0
Interrupt on MR0
1
Reset on MR0
2
Stop on MR0
3
Interrupt on MR1
4
Reset on MR1
5
Stop on MR1
6
Interrupt on MR2
7
Reset on MR2
8
Stop on MR2
9
Interrupt on MR3
10
Reset on MR3
11
Stop on MR3
Timer0 and Timer1
When one, an interrupt is generated when MR0 matches the value in the TC. When
zero this interrupt is disabled.
When one, the TC will be reset if MR0 matches it. When zero this feature is disabled.
When one, the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches
the TC. When zero this feature is disabled.
When one, an interrupt is generated when MR1 matches the value in the TC. When
zero this interrupt is disabled.
When one, the TC will be reset if MR1 matches it. When zero this feature is disabled.
When one, the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches
the TC. When zero this feature is disabled.
When one, an interrupt is generated when MR2 matches the value in the TC. When
zero this interrupt is disabled.
When one, the TC will be reset if MR2 matches it. When zero this feature is disabled.
When one, the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches
the TC. When zero this feature is disabled.
When one, an interrupt is generated when MR3 matches the value in the TC. When
zero this interrupt is disabled.
When one, the TC will be reset if MR3 matches it. When zero this feature is disabled.
When one, the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches
the TC. When zero this feature is disabled.
LPC2119/2129/2194/2292/2294
Description
218
Preliminary User Manual
Reset
Value
0
0
0
0
0
0
0
0
0
0
0
0
May 03, 2004
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