Miscellaneous Register Group - Philips LPC2194 User Manual

Philips Semiconductors
ARM-based Microcontroller

MISCELLANEOUS REGISTER GROUP

Table 177 summarizes the registers located from 0 to 7 of A[6:2]. More detailed descriptions follow.
Table 177: Miscellaneous Registers
Address Name
0xE0024000 ILR
0xE0024004 CTC
0xE0024008 CCR
0xE002400C CIIR
0xE0024010 AMR
0xE0024014 CTIME0
0xE0024018 CTIME1
0xE002401C CTIME2
Interrupt Location (ILR - 0xE0024000)
The Interrupt Location Register is a 2-bit register that specifies which blocks are generating an interrupt (see Table 178). Writing
a one to the appropriate bit clears the corresponding interrupt. Writing a zero has no effect. This allows the programmer to read
this register and write back the same value to clear only the interrupt that is detected by the read.
Table 178: Interrupt Location Register Bits (ILR - 0xE0024000)
ILR Function
0 RTCCIF
1 RTCALF
Clock Tick Counter (CTC - 0xE0024004)
The Clock Tick Counter is read only. It can be reset to zero through the Clock Control Register (CCR). The CTC consists of the
bits of the clock divider counter.
Table 179: Clock Tick Counter Bits (CTC - 0xE0024004)
CTC Function
0 Reserved
Clock Tick
15:1
Counter
Real Time Clock
Size
Interrupt Location. Reading this location indicates the source of an
2 interrupt. Writing a one to the appropriate bit at this location clears the
associated interrupt.
15 Clock Tick Counter. Value from the clock divider.
4 Clock Control Register. Controls the function of the clock divider.
Counter Increment Interrupt. Selects which counters will generate an
8
interrupt when they are incremented.
8 Alarm Mask Register. Controls which of the alarm registers are masked.
32 Consolidated Time Register 0
32 Consolidated Time Register 1
32 Consolidated Time Register 2
When one, the Counter Increment Interrupt block generated an interrupt. Writing a one to this bit
location clears the counter increment interrupt.
When one, the alarm registers generated an interrupt. Writing a one to this bit location clears the
alarm interrupt.
Reserved, user software should not write ones to reserved bits. The value read from a reserved bit
is not defined.
Prior to the Seconds counter, the CTC counts 32,768 clocks per second. Due to the RTC Prescaler,
these 32,768 time increments may not all be of the same duration. Refer to the Reference Clock
Divider (Prescaler) description for details.
LPC2119/2129/2194/2292/2294
Description
Description
Description
246
Preliminary User Manual
Access
RW
RO
RW
RW
RW
RO
RO
RO
May 03, 2004