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Connecting Crystal Oscillator
The following diagram shows the connection of the 75 kHz crystal oscillator to the device's crystal oscillator
pins (X
, X
).
IN
OUT
The oscillation signal is supplied to the clock generator, reference frequency divider, and other sub-systems to
generate the various CPU timing signals, reference frequency, and other signals. The power supply for the
crystal oscillator circuit is the voltage (V
stabilizes the crystal oscillation and reduces the current consumption.
Note 17: Use a crystal oscillator with a low CI value and with good startup characteristics.
System Reset
The system is reset when a low level is applied to the RESET pin, or when the voltage supplied to the V
pin goes from 0 V to 1.8 V or more (a power on reset). Following a system reset, the program starts from address
0 after a standby period of 100 ms.
As the power on reset function is typically used, fix the RESET pin to the high level.
Note 18: During a system reset and during the standby period following the reset, the LCD common and segment
outputs are fixed at the low level.
Note 19: After a system reset, the internal ports shown in the following table are fixed at the specified levels. The
states of the other ports after a reset are undefined. Therefore, initialize the ports in the program when
necessary.
Fixed Internal Ports
Ports Set to "0"
SC
bit ( L16), MANUAL bit ( L17)
ON
I/O, POL, UNLOCK bits ( L18)
DO2 control port ( L19)
BUZR ports ( L1A, L1B)
Test ports ( L1F, L27, L2FF)
CKSTP MODE bit ( L27)
DA/AD control ports ( L20, L22)
SIO control ports ( L23, L24)
Timer port ( K27)
V
OFF, KSSTP bits ( L2FF)
LCD
I/O-1~I/O-7 I/O control ports ( L39~ L3F)
1.5 V typ.) supplied by the built-in constant voltage circuit. This
XT
Ports Set to "1"
Reference port ( L15)
MUTE bit ( L18)
IF
1/
2
,
IF1/
IN1
,
IF2/
DISP OFF bit ( L2FF)
SEG I/O bit
(SEG/I/O switching bits: L2F2~ L2FD)
18
IN2
bits ( L16)
TC9314F
DD
2003-07-03
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