Toshiba TC9314F Manual page 15

Mnemonic
TMTR r, M
TMFR r, M
TMT M, N
TMF M, N
TMTN M, N
TMFN M, N
SKP
SKPN
CALL ADDR
1
RN
RNS
JUMP ADDR
1
SHRC M
RORC M
XCH M
DAL ADDR , r
2
WAIT P
CKSTP
NOOP
Note 12: Among 10 bits of the program memory address assigned by DAL instruction, the lower rank of 4 bits
become indirect addressing based on the content of general register.
DAL instruction executing time is 80 s. (2 machine cycles)
Note 13: MVGS instruction executing time is 80 s. (2 machine cycles)
Explanation of Function
Test general register bits
by memory bits, then skip
*
if all bits specified are
true
Test general register bits
by memory bits, then skip
*
if all bits specified are
false
Test memory bits, then
skip if all bits specified
*
are true
Test memory bits, then
skip if all bits specified
*
are false
Test memory bits, then
* not skip if all bits
specified are true
Test memory bits, then
* not skip if all bits
specified are false
* Skip if carry flag is set
* Skip if carry flag is reset
Call subroutine
Return to main routine
Return to main routine
*
and skip unconditionally
Jump to the address
specified
Shift memory bits to right
direction with carry
Rotate memory bits to
right direction with carry
Exchange memory bits
mutually
Load program memory in
page 0 to DATA register
At P "0" H, the condition
is CPU waiting (Soft wait
mode)
At P "1" H, except for
clock generator, all
function is waiting (Hard
wait mode)
Clock generator stop
No operation
Explanation of Operation
Skip if r [N (M)] all "1"
Skip if r [N (M)] all "0"
Skip if M (N) all "1"
Skip if M (N) all "0"
Skip if M (N) not all "1"
Skip if M (N) not all "0"
Skip if (CY) 1
Skip if (CY) 0
STACK (PC) 1 and
PC ADDR
1
PC (STACK)
PC (STACK) and skip
PC ADDR
1
0 (M) b3 (M) b2
(M) b1 (M) b0 (CY)
(M) b3 (M) b2
(M) b1 (M) b0
(CY)
(M) b3 (M) b0,
(M) b2 (M) b1
DATA [ADDR (r)]
2 P
in page 0
Wait at condition P
Stop clock generator
according to MODE
condition
15
TC9314F
Machine Language (16 bit)
IC A B
(6 bit) (2 bit) (4 bit)
010000 D D
R C
010001 D D
R C
110101 D D
R C
110111 D D
R C
110100 D D
R C
110110 D D
R C
111111 00
111111 01
100 ADDR (13 bit)
1
111111 10
111111 11
101 ADDR (13 bit)
1
111111 D D
R C
111111 D D
R C
111111 D D
R C
111110 ADDR (6 bit)
2
111111 P
111111
111111
2003-07-03
C
(4 bit)
R
N
R
N
N
N
N
N
0011
0011
0011
0011
0000
0001
0110
R
N
0100
0101
1111