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1/0
Pin
Pin
Symbol
No.
1
0
Inverter output terminal for oscillation
OSCO
Inverter input terminal for oscillation
2
I
OSCI
Error compensation data input method setting
I
3
EF
terminal
I
4
EDO
Shutter speed control terminal
(with pull-up resistor)
I
5
ED1
(Details g iven later)
I
6
ED2
S hutter mode setting terminal
I
7
SMD1
(with pull-up resistor) (Details g iven later)
8
GND
-
Vss
S hutter mode setting terminal
I
9
SMD2
(with pull-up resistor) (Details g iven later)
0
1 0
Power control terminal of external ROM
XVCT
1 1
I
D1
Data input
1 2
I
D2
terminal when
using external ROM
1 3
I
D3
ROM
I
1 4
D4
1 5
0
A5
1 6
0
A4
0
1 7
A3
Address output terminal to external ROM
AO
1 8
0
1 9
0
A1
20
0
A2
-
LH1 power supply
21
VEE
Pre-charge gate pulse output terminal
22
0
PG
Clock output terminal for CCD horizontal
23
LH1
0
register final step (9 V amplitude output)
-
Power terminal
24
Voo1
-
25
Power terminal (for H 1 and H2)
Voo2
Clock pulse output terminal for CCD
26
0
H 1
horizontal register drive
Clock pulse output terminal for CCD
27
0
H2
horizontal register drive
28
GND (for H1 and H2)
Vss2
-
CCD electric charge throwaway pulse
29
0
XSUB
output terminal
Clock pulse output terminal for CCD
0
30
XV2
vertical register drive
Clock pulse output terminal for CCD
31
0
XV1
vertical register drive
CCD sensor electric charge readout pulse
32
0
XSG1
output terminal
Clock pulse output terminal for CCD
33
0
XV3
vertical register d rive
:
*1 : L : Field accumulation
*2 : H
Frame accumulation
Pin Description
(with pull-up resistor)
Normally "L"
When not
using external
Normally "L"
(with pull-down
* 1
resistor)
L: NTSC H: PAL
( - 4
V)
Table 2-2. Timing IC Terminal Specifications
1/0
Pin
Pin
Symbol
No.
34
0
XSG2
35
0
XV4
I
36
TEST2
0
37
CLD
38
0
XSHP
39
0
XSHD
-
40
VSS1
41
0
XSP1
42
0
XSP2
0
43
XSH1
44
0
XSH2
45
0
XDL1
* 2
46
0
XDL2
47
0
BFG
48
0
CLP1
0
49
C LP2
50
0
CLP3
51
0
C LP4
52
0
PBLK
53
0
ID
54
0
WEN
55
I
GM
-
56
V oo1
0
57
CL
I
58
PS
I
59
HD
I
60
VD
I
61
HTSG
I
62
TEST
63
0
XCK
I
64
CK
- 4- 1 1 -
Pin Description
CCD sensor electric charge readout
pulse output terminal
Clock pulse output terminal for CCD
vertical register drive
S hould not be connected
4
fsc clock output
Pre-charge level • sample and hold pulse
Data • sample and hold pulse
GND
Colour separation sample and hold pulse
Colour separation sample and hold pulse
Selection sample and hold pulse
Selection sample and hold pulse
Delay line clock (mosaic mode)
colour separation sample and hold pulse (stripe)
Delay line clock (mosaic mode)
selection sample and hold pulse (stripe)
Encoder • chroma modulator pulse
Defective address pulse when G3
Clamp pulse output terminal
Pre-blanking cleaning pulse
Line discriminating terminal (mosaic mode) :
"L" (stripe mode)
Write enable terminal (only for low speed
shutter)
(Details given later)
L : normal mode, H : G3 mode
(with pull-down resistor)
Power terminal
1 /2 frequency-divided output terminal
of input clock from CK
Electronic shutter speed data input
L : serial input
H : parallel input
(with pull-up resistor)
Horizontal sync signal input terminal
Vertical sync signal input terminal
XSG1 and 2 control
L : XSG 1 , 2 stop
H : XSG 1 and 2 generation
(with pull-up resistor)
Test terminal, L : normal mode, H : test mode
(with pull-down resistor)
Clock inverted output terminal fed from CK
I nverter input terminal for duty control
(IC main clock input)
I
I
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