NEC UPD98413 User Manual page 94

(3) Performance monitoring counter
The 32-bit performance monitoring counters that totalize the number of times each event for a cell reception has
occurred are provided to each port as shown in Table 3-16. The host can recognize these counts by reading
data from the register.
Counter Type
Line monitor B1 error counter
counters
B2 error counter
B3 error counter
Line REI counter
Path REI counter
Cell counters Transmit valid cell counter
Receive valid cell counter
Receive idle cell counter
HEC error drop cell counter
HEC correct cell counter
Receive FIFO full drop cell
counter
Packet Transmit valid packet counter
counters
Transmit abort packet counter
Transmit FIFO underflow packet
counter
Receive valid packet counter
Receive abort packet counter
Receive address error packet
counter
Receive FCS error packet
counter
Receive FIFO overflow packet
counter
Receive long packet counter
Receive short packet counter
Note: The HEC drop cell counter and HEC Correct counter operate differently depending on the mode setting of
HEC error control by the MDATMR registers.
94
CHAPTER 3 FUNCTIONAL OUTLINE
Table 3-16. Performance Monitoring Counters
Counter Name
Number of bits or frames detected B1 errors
Number of bits or frames detected B2 errors
Number of bits or frames detected B3 errors
Number of bits or frames detected Line REI errors
Number of bits or frames detected Path REI errors
Number of cells transmitted from the transmit FIFO to the line.
Number of received cells transferred from the receive FIFO to the
ATM interface
Number of received invalid cells dropped internally
Number of cells discarded due to the HEC verification
Number of cells modified due to the HEC verification
Number of dropped cells due to receive FIFO overflow
Number of packets or bytes transmitted from the transmit FIFO to the
line
Number of abort packets transmitted from the transmit FIFO to the
line
Number of abort packets transmitted due to transmit FIFO underflow
Number of received packets or bytes transferred from the receive
FIFO to the POS interface
Number of received abort packets transferred from the receive FIFO
to the POS interface
Number of address error packets dropped internally
Number of FCS error packets transferred from the receive FIFO to the
POS interface
Number of packets which the receive FIFO overflow occurs while a
packet is being received
Number of long packets due to long size packet error
Number of short packets due to short size packet error
PRELIMINARY
Count Item
Note
Note
NEC confidential and Proprietary