NEC UPD98413 User Manual page 157

(4) Usage of Event Detection register and Event Termination registers
These registers indicate the statuses of the
these registers, the CPU can check the occurrence and end of an event.
Figure 4-28 shows an example in which event LOS is detected by using the DSLER and TSLER registers. Each
mask register is cleared so that the setting of the bits of the DSLER and TSLER registers is reflected on the ICR
register. Similarly, the masking of the ICR register is cleared so that setting of the bits of the ICR register is
reflected on the interrupt signal.
If the LOS event is detected, the LOS bit of the DSLER register and the DSLER bit of the ICR register are set to
1, and the INT_B signal is asserted active. The CPU that receives an interrupt signal reads the ICR and DSLER
registers, in that order, to check the interrupt cause. When the CPU clears the LOS bit of the DSLER register,
the DSLER bit of the ICR register is also cleared to 0, and INT_B is deasserted inactive. The LOS bit of the
DSLER register remains set to 1 until it is cleared by the CPU.
If the LOS event ends, the LOS bit of the TSLER register and TSLER bit of the ICR register are set, and INT_B is
asserted active again. When the LOS bit of the TSLER register is cleared, INT_B is deasserted inactive. The
LOS bit of the TSLER register remains set to 1 until it is cleared by the CPU.
The SSLER register indicates the status of an event. The LOS bit of this register is set to 1 since LOS is
detected until it ends. The setting the bits of this register is not used as an interrupt cause. If both the TSLER
and TSLER bits of the ICR register are set when the register is read by the CPU, whether the LOS event has
been detected and ended, or whether it has ended and then has been detected, can be determined by checking
the status of the LOS bit of the SSLER register.
Figure 4-28. Bit Operations of DSLER and TSLER Registers
LOS Event
DSLER [LOS Bit]
TSLER [LOS Bit]
SSLER [LOS Bit]
Cleaed by CPU
Interrupt Signal
(INT_B)
CHAPTER 4 INTERFACES
25 events: Event detection and termination registers. By using
PRELIMINARY
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