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(b) HEC error control
While cell synchronization is established, a one-bit error of a cell header is corrected and errors of multiple bits
are detected by means of header error control (HEC). As a result of the header error control processing, only the
valid cell that includes error correction and which does not offer error correction in the header is stored into the
receive FIFO and transferred to the ATM interface. Figure 3-18 shows the status transition of header error
control.
Figure 3-18. HEC Check Status Transition in Cell Synchronization Status
From preceding synchronization
status to cell synchronization status
•
An error of only one bit is corrected in the correction mode and then the detection mode is set.
•
HEC errors are continuously monitored in the correction mode. If errors are detected
status is changed from the cell synchronization status to the hunting status.
•
Whether a 1-bit error is corrected when it has been detected, and the condition in which the mode is changed
from detection mode to correction mode can be specified by using the MDATMR register.
CHAPTER 3 FUNCTIONAL OUTLINE
Cell synchronization status
Multiple bit error detection
(Cell dropped)
No error
(Cell passes)
No error for
Correction mode
(Cell passes)
1-bit error detection
(Error is corrected and cell is passed.)
Cell is dropped without correcting error.
Table 3-11. HEC Error Control Mode
Execution of 1-bit error correction
of header
None
Correction executed (default)
ε
Number of stages (
) for changing
mode from detection to correction
1 (default)
2
4
PRELIMINARY
(SYNC)
Error detection
Cell dropped
ε
times
Detection mode
MDATMR Register
HECCM Bit
1
0
MDATMR Register
HECDC[1:0] Bits
00
01
10
From cell synchronization
status to hunting status
α
times in a row, the
NEC confidential and Proprietary
63
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