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(3) Change in bit of detailed causes register and interrupt cause register
The condition under which each bit of the detailed cause register is set or reset differs, as shown below.
Table 4-11. Set and Reset Conditions of Detailed Cause Register and interrupt cause register
Register
DGE
DSLER register
DPPER register
DAPER register
DAPET register
TGE
TSLER register
TPPER register
TAPER register
156
CHAPTER 4 INTERFACES
Set Condition
Event detection
Event termination
PRELIMINARY
Reset Condition
Cleared by CPU
Cleared by CPU
NEC confidential and Proprietary
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