Instruction Register; Preliminary - NEC UPD98413 User Manual

6.6 Initializing TAP Controller
The TAP controller is initialized as follows:
(1) The TAP controller is not initialized by the operation of system input such as system reset.
(2) The TAP controller enters the Test-Logic-Reset controller state at the fifth rising edge of the JCK pin signal
(while the JMS pin signal is held high).
(3) The TAP controller asynchronously enters the Test-Logic-Reset state when the JRST_B signal is input.

6.7 Instruction Register

This register is defined as follows (see Section 6.2).
(1) The instruction shifted and input to the instruction register is latched so that it changes only in the Update-IR
and Test-Logic-Reset controller states.
(2) Data is not inverted since it has been serially input to the instruction register until it is serially output.
(3) A fixed binary pattern data "01" (with LSB (Least Significant Bit) being "1") is loaded to this register cell in the
Capture-IR controller state.
(4) A fixed binary pattern data "01" (with LSB (Least Significant Bit) being "1") is loaded to this register cell in the
Test-Logic-Reset controller state.
(5) While this register is read, data is output from the JDO pin, starting from the LSB to the MSB, at each falling
edge of the JCK pin signal.
The JTAG boundary scan circuit of the mPD98414 can support only the following three instructions depending on
the data set to the instruction register.
• BYPASS instruction
• EXTEST instruction
• SAMPLE/PRELOAD instruction
Instruction Register
D1
0
0
1
1
316
CHAPTER 6 JTAG BOUNDARY SCAN
Supported Instruction
D0
0
EXTEST instruction
1
SAMPLE/PRELOAD instruction
0
Unused (BYPASS instruction)
1
BYPASS instruction

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