NEC 78K0 User Manual page 6

Page
Throughout Addition of products
µ
PD78F0148(A1), 780143(A2), 780144(A2), 780146(A2), 780148(A2)
Under development → Under mass production
µ
PD780143, 780144, 780146, 780148, 78F0148, 780143(A), 780144(A), 780146(A), 780148(A), 78F0148(A),
780143(A1), 780144(A1), 780146(A1), 780148(A1)
Modification of names of the following special function registers (SFRs)
• Ports 0 to 7, and 12 to 14 → Port registers 0 to 7, and 12 to 14
p.38 Addition of Cautions 3 and 4 to 1.4 Pin Configuration (Top View)
p.40 Modification of 1.5 K1 Family Lineup
p.45 Modification of outline of timer in and addition of Remark to 1.7 Outline of Functions
p.47 Addition of Table 2-1 Pin I/O Buffer Power Supplies
pp.55, 56 Modification of descriptions in 2.2.12 AV
Modification of the following contents in Table 2-2 Pin I/O Circuit Types
pp.57, 58
• Modification of recommended connection when P60 to P63 are not used
• Modification of I/O circuit type of P62 and P63
• Addition of Note to AV
• Modification of recommended connection when V
Modification of Figure 3-1 Memory Map (
pp.62 to 66
p.76 Modification of Figure 3-14 Data to Be Saved to Stack Memory
p.77 Modification of Figure 3-15 Data to Be Restored from Stack Memory
p.90 Modification of [Description example] in 3.4.4 Short direct addressing
pp.93 to 95 Addition of [Illustration] to 3.4.7 Based addressing, 3.4.8 Based indexed addressing, and 3.4.9 Stack
addressing
p.96 Addition of Table 4-1 Pin I/O Buffer Power Supplies
p.98 Modification of Table 4-3 Port Configuration
pp.108, 111, 112, Modification of Figure 4-11 Block Diagram of P20 to P27, Figure 4-14 Block Diagram of P40 to P47,
114, 115 Figure 4-15 Block Diagram of P50 to P57, Figure 4-17 Block Diagram of P64, P65, and P67, and Figure
4-18 Block Diagram of P66
p.118 Addition of Remark to Figure 4-21 Block Diagram of P130
p.123 Deletion of input switch control register (ISC) from and addition of port registers (P0 to P7, P12 to P14) to 4.3
Registers Controlling Port Function
p.124 Modification of setting of output latch of P40 to P47, P50 to P57, P64, P65, and P67 in and addition of Note 2
to Table 4-5 Settings of Port Mode Register and Output Latch When Using Alternate Function
p.128 Partial modification of descriptions in 4.4.1 (1) Output mode, 4.4.3 (1) Output mode, and (2) Input mode
p.129 Addition of Caution to 5.1 External Bus Interface
p.132 Addition of Note to Figure 5-2 Format of Memory Expansion Mode Register (MEM)
p.134 Addition of Caution 2 to Figure 5-4 Format of Memory Expansion Wait Setting Register (MM)
p.139 Addition of Remark to Figure 5-8 External Memory Read Modify Write Timing
p.142 Modification of Figure 6-1 Block Diagram of Clock Generator
p.143 Addition of Note to 6.3 (1) Processor clock control register (PCC)
6
Major Revisions in This Edition (1/3)
Description
, 2.2.15 REGC, and 2.2.20 V
REF
REF
µ
PD780143) to Figure 3-5 Memory Map (
*
User's Manual U15947EJ2V0UD
(flash memory versions only)
PP
is not used
PP
µ
PD78F0148)