Operation Timing Of Bit Shift Detection Function By Busy Signal (When Busylv0 = 0) - NEC 78K0 User Manual

(c) Bit shift detection by busy signal
During automatic transmission/reception, a bit shift of the serial clock of the slave device may occur
because noise is superimposed on the serial clock signal output by the master device. Unless the strobe
control option is used at this time, the bit shift affects transmission of the next byte. In this case, the
master can detect the bit shift by checking the busy signal during transmission by using the busy control
option.
A bit shift is detected by using the busy signal as follows:
The slave outputs the busy signal after the rising of the eighth serial clock during data
transmission/reception (to not keep transmission/reception waiting by the busy signal at this time, make
the busy signal inactive within 2 clocks).
The master samples the busy signal in synchronization with the falling edge of the serial clock if bit 2
(ERRE0) of serial status register 0 (CSIS0) is set to 1. If a bit shift does not occur, all the eight serial
clocks that have been sampled are inactive. If the sampled serial clocks are active, it is assumed that a
bit shift has occurred, error processing is executed (by setting bit 1 (ERRF0) of serial status register 0
(CSIS0) to 1, and communication is suspended and an interrupt request signal (INTACSI) is output).
Although communication is suspended after completion of 1-byte data communication, slave signal
output, wait due to the busy signal, and wait due to the interval time specified by ADTI0 are not executed.
If ERRE0 = 0, ERRF0 cannot become 1 even if a bit shift occurs.
Figure 17-28 shows the operation timing of the bit shift detection function by the busy signal.
Remark The bit error function is valid both in the master mode and slave mode. The setting of ERRE0
is valid even when BUSYE0 = 0.
Figure 17-28. Operation Timing of Bit Shift Detection Function by Busy Signal (When BUSYLV0 = 0)
SCKA0
(Master)
SCKA0
(Slave)
SOA0
D7 D6 D5 D4 D3 D2 D1 D0
SIA0 D7 D6 D5 D4 D3 D2 D1 D0
BUSY0
ACSIIF
CSIAE0
ERRF0
ACSIIF: Interrupt request flag
CSIAE0: Bit 7 of serial operation mode specification register 0 (CSIMA0)
ERRF0: Bit 1 of serial status register 0 (CSIS0)
416
CHAPTER 17 SERIAL INTERFACE CSIA0
*
D7 D7 D6 D5 D4 D3 D2 D1
D7 D7 D6 D5 D4 D3 D2 D1
Busy not detected
User's Manual U15947EJ2V0UD
Bit shift due to noise
D0
D0
Error interrupt request
generated
Error detected