Block Diagram Of Clock Generator - NEC 78K0 User Manual

Main OSC
control
register
(MOC)
MCC CLS
MSTOP
STOP
X1
X1 oscillator
f
XP
X2
Ring-OSC
oscillator
f
Mask option
1: Cannot be stopped
0: Can be stopped
RSTOP
Ring-OSC mode
register (RCM)
142
CHAPTER 6 CLOCK GENERATOR
Figure 6-1. Block Diagram of Clock Generator
Internal bus
Main clock
mode register
(MCM)
MCS MCM0 OSTS2
stabilization time counter
MOST
11
f
X
Operation
clock switch
R
Prescaler
8-bit timer H1,
watchdog timer
Internal bus
User's Manual U15947EJ2V0UD
Oscillation
stabilization time
select register
(OSTS)
OSTS1 OSTS0 CLS CSS PCC2
3
4
X1 oscillation
Oscillation
stabilization
MOST MOST MOST MOST
time counter
13 14 15 16
status
register
(OSTC)
Prescaler
f f f f
X X X X
2 3 4
2 2 2 2
*
Prescaler
Clock to peripheral
hardware
Processor clock
control register
(PCC)
PCC1 PCC0
Control signal
Controller
C
CPU clock
P
(f )
CPU
U
f
CPU
Watch clock,
clock output
function
Subsystem XT1
1/2
clock oscillator
XT2
f
XT
FRC