NEC 78K0 User Manual page 420

(1) Remainder data register 0 (SDR0)
SDR0 is a 16-bit register that stores a remainder. This register stores 0 in the multiplication mode and the
remainder of an operation result in the division mode.
This register can be read by an 8-bit or 16-bit memory manipulation instruction.
RESET input clears this register to 0000H.
Address: FF60H, FF61H
Symbol
SDR0 SDR SDR SDR
015 014 013
Cautions 1. The value read from SDR0 during operation processing (while bit 7 (DMUE) of
multiplier/divider control register 0 (DMUC0) is 1) is not guaranteed.
2. SDR0 is reset when the operation is started (when DMUE is set to 1).
420
CHAPTER 18 MULTIPLIER/DIVIDER
Figure 18-2. Format of Remainder Data Register 0 (SDR0)
After reset: 0000H R
FF61H (SDR0H)
SDR SDR SDR SDR
012 011 010 009
User's Manual U15947EJ2V0UD
FF60H (SDR0L)
SDR SDR SDR SDR SDR
008 007 006 005 004
*
SDR SDR SDR SDR
003 002 001 000