Operation Timing When Busy Control Option Is Used (When Busylv0 = 1); Busy Signal And Wait Release (When Busylv0 = 1) - NEC 78K0 User Manual

8-bit single-chip microcontrollers
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Figure 17-25. Operation Timing When Busy Control Option Is Used (When BUSYLV0 = 1)
SCKA0
SOA0
D7
D6 D5 D4 D3 D2 D1 D0
SIA0
D7 D6 D5 D4 D3 D2 D1 D0
BUSY0
ACSIIF
TSF0
Remark
ACSIIF: Interrupt request flag
TSF0:
When the busy signal becomes inactive, waiting is released. If the sampled busy signal is inactive,
transmission/reception of the next 8-bit data is started at the falling edge of the next serial clock.
Because the busy signal is asynchronous with the serial clock, it takes up to 1 clock until the busy signal
is sampled, even if made inactive by the slave. It takes 0.5 clock until data transfer is started after the
busy signal was sampled.
To accurately release waiting, the slave must keep the busy signal inactive at least for the duration of 1.5
clock.
Figure 17-26 shows the timing of the busy signal and releasing the waiting. This figure shows an
example in which the busy signal is active as soon as transmission/reception has been started.
Figure 17-26. Busy Signal and Wait Release (When BUSYLV0 = 1)
SCKA0
SOA0
D7
SIA0
D7 D6 D5 D4 D3 D2 D1 D0
BUSY0
(active-high)
414
CHAPTER 17 SERIAL INTERFACE CSIA0
Wait
Bit 0 of serial status register 0 (CSIS0)
D6 D5 D4 D3 D2 D1 D0
If made inactive
immediately after
sampled
User's Manual U15947EJ2V0UD
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Busy input released
Busy input valid
*
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1.5 clocks (min.)
Wait
Busy input released
Busy input valid

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