I/O Interrupt Controller 8259A - Sanyo MBC-550 Series User Manual

I/O Interrupt Controller 8259A
8259A control interrupts. 8259A has eight levels of
interrupt request pins. Interrupt requests arriving at
the respective pins are detected when the signal goes
high or low.
Pin Vector
Interval timer (established to 10 msec in IRO 248(F8)
period)
Interval timer 1 (clock counter)
249(F9)
IR1
USART Ready (RS232C) 250(FA) IR2
USART Rx Ready (keyboard) 251(FB)
IR3
252(FC)
IRiJ
Printer Ready
253CFD) Floppy disk controller
IR5
IR6 25MFE) 8087 digital data processor
User interrupt (external bus IR7) (*1)
*1 Negative logic
255(FF)
IR7
The priorities of pins are fixed to the order of IRO
(high) to IR7 (low).
Operation Command Word (OCW) 1 changes the priorities.
Of IRO to IR7, only IR1 to IR3 are associated with
BIOS.
Pins other than IR1 to IR3 are masked by the interrupt
mask register (MR) in 8259. The IMR can be read/writ­
ten by performing Read/Write command on I/O address 02.
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