Multiport Ethernet Phy - Siemens ERTEC200 Manual

Enhanced real-time ethernet controller
Table of Contents

Advertisement

9

Multiport Ethernet PHY

A 2-fold multiport PHY (Physical Layer Transceiver) that supports the following transfer modes is integrated in the
ERTEC 200:
10BASE-T
100BASE-TX
100BASE-FX
These transfer modes are available separately for each port and can be set differently.
The PHY is compatible with the following standards:
IEEE802.3
IEEE802.3u
ANSI X3.263-1995
ISO/IEC9314
The data interface with the Ethernet MACs takes place via MII. The management interface can be addressed via the
MDIO interface (SMI interface). The 25 MHz clock supply is to be provided as follows:
25 MHz quartz on the ERTEC 200 pins CLKP_A and CLKP_B or
25 MHz clock on the ERTEC 200 pin CLKP_A
In addition to the basic functionalities of the transfer modes 10BASE-T, 100BASE-TX, and 100BASE-FX, the PHYs also
support:
Auto-negotiation
Auto-crossing
Auto-polarity
The following PHY registers can be assigned via the SMI interface:
Register-Nr.
0
1
2
3
4
5
6
7
8 - 15
16
17
18
19
20 - 26
27
28
29
30
31
For an exact description of the PHY registers, refer to /13/.
During a hardware reset or when leaving the Power Down State (Px_PHY_ENB = 1), an initial configuration is set on an
internal Config port of the PHY. This configuration can be modified later in the PHY register set. The internal Config port
comprises the following parameter assignment, which at present can be permanently set or set via software in the
PHY_CONFIG system control register.
Copyright © Siemens AG 2007. All rights reserved.
Technical data subject to change
Description
Basic-Control-Register
Basic-Status-Register
PHY-Identifier 1
PHY-Identifier 2
Auto Negotiation Advertisement Register
Auto Negotiation Link Partner Ability Register
Auto Negotiation Expansion Register
Next Page Timing Register
Non-supported registers
Silicon Revision Code
ModeControl/ Status Register
Special Modes
SMII Configuration Status Register
Reserved
Control/Status Indication Register
Special Internal Testability Register
Interrupt Source Register
Interrupt mask register
PHY Special Control/Status Register
88
Group
Basic
Basic
Extended
Extended
Extended
Extended
Extended
Extended
------
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
ERTEC 200 Manual
Version 1.1.0

Hide quick links:

Advertisement

Table of Contents
loading

Table of Contents