Watchdog Registers; Address Assignment Of Watchdog Registers; Watchdog Register Description; Table 12: Overview Of Wd Registers - Siemens ERTEC200 Manual

4.5.6

Watchdog Registers

The watchdog registers are 32 bits in width. For read/write access of the watchdog registers to be meaningful, a 32-bit
access is required. However, a byte-by-byte write operation is not intercepted by the hardware.
To prevent the watchdog registers from being written to inadvertently, e.g., in the event of an undefined computer crash,
the writable watchdog registers are provided with write protection. The upper 16 bits of the registers are so-called key
bits. In order to write a valid value in the lower 16 bits, the key bits must be set to 0x 9876 yyyy (yyyy is the 16-bit value
to be written).
4.5.7

Address Assignment of Watchdog Registers

Register Name Offset Address Address Area
CTRL/STATUS
RELD0_LOW
RELD0_HIGH
RELD1_LOW
RELD1_HIGH
WDOG0
WDOG1

Table 12: Overview of WD Registers

4.5.8

Watchdog Register Description

CTRL/STATUS
Description Control/status register Configuration and control bits for the watchdog.
Bit No. Name
0 Run/xStop_V0
1 Run/xStop_Z1
2 Load(Trigger)
3 Status_Counter 0
4 Status_Counter 1
15-5 Reserved
31-16 Key bits
Copyright © Siemens AG 2007. All rights reserved.
Technical data subject to change
Watchdog
(Base Address 0x4000_2100)
0x0000 4 bytes
0x0004 4 bytes
0x0008 4 bytes
0x000C 4 bytes
0x0010 4 bytes
0x0014 4 bytes
0x0018 4 bytes
R/W Addr.: 0x4000_2100
Description
Enable/disable watchdog counter 0:
0: Watchdog counter 0 disabled
1: Watchdog counter 0 enabled
Note: If this bit = 0, the WDOUT0_n output of the ERTEC 200 is active (0),
the interrupt of the watchdog (WDINT) is "0", and the status bit of counter 0
(Bit 3) is "0".
Enable/disable watchdog counter 1:
0: Watchdog counter 1 disabled
1: Watchdog counter 1 enabled
Note: If this bit = 0, the WDOUT1_N output of the ERTEC 200 is passive (1)
and the status bit of counter 1 (Bit 4) is "0".
Watchdog trigger (load watchdog counters 0 and 1 with the value of the
reload registers):
0: Do not trigger watchdog
1: Trigger watchdog
While this bit can be read back, it only has an
Writing a value of 1 to this bit is sufficient to trigger
0/1 edge is not needed.
The trigger signal acts on both watchdog co
Watchdog status counter 0 (writing is ignored):
0: Watchdog counter 0 has not expired
1: Watchdog counter 0 has expired
Note: This bit can only be read as '1' if Run/xStop_Z0 is active (1).
Watchdog status counter 1 (writing is ignored):
0: Watchdog counter 1 has not expired
1: Watchdog counter 1 has expired
Note: This bit can only be read as '1' if Run/xStop_Z1 is active (1).
Not relevant (read=0)
Key bits for writing to this register (read=0).
If bits 31-16=9876h, writing of bits 0-4 of this register has an effect;
otherwise, no effect.
Access Default
R/W 0x00000000
R/W 0x0000FFFF
R/W 0x0000FFFF Reload register 0_High Bits 16-31
R/W 0x0000FFFF
R/W 0x0000FFFF Reload register 1_High Bits 20-35
R 0xFFFFFFFF
R 0xFFFFFFFF
Default: 0x0000_0000
effect at the instant of writing.
unters.
46
Description
Control/status register WD
Reload register 0_Low Bits 0-15
Reload register 1_Low Bits 4-19
Watchdog timer 0 value register
Watchdog timer 1 value register
the watchdog counter; a
ERTEC 200 Manual
Version 1.1.0